1. Field of the Invention
The present invention relates to a data processor and, more particularly, to a data processor having a bus controller for controlling a plurality of buses independently each other.
2. Description of the Related Art
Recently, a data processor having a central processing unit (CPU) and a plurality of peripheral input/output (I/O) circuits formed in one chip has been widely used in a microcomputer system. In this microcomputer system, a memory storing a string of instructions is provided outside the data processor as an external memory. The external memory and the internal peripheral I/O circuits are accessed by CPU to fetch instructions from the external memory and to read or write data from or into the I/O circuits. The peripheral I/O circuits serve as a pulse counter, a serial data receive/transmit circuit, and so on, and have respective registers each mapped at specific or unique addresses. The addresses of the external memory area and the the peripheral I/O circuits are discriminated on a memory map.
Referring now to FIG. 9, a microcomputer system according to the prior art includes a data processor or a microcomputer 12 and an external memory 100 which are interconnected through an external bus 95. The microcomputer 12 makes access to the external memory 100 by use of a group of external bus cycle control signals 96.
The microcomputer 12 comprises a CPU 20, a data path circuit 25, a bus controller 35, and peripheral I/O circuits 40-49. The CPU 20 outputs a set of request signals 93 to the bus controller 35 and receives a set of acknowledge signals 94 from the bus controller 35. The CPU 20 is further connected to the data path circuit 26 through an address bus 70, an data output bus 71, an instruction bus 72, and an data input bus 73. The CPU 20 outputs an address and write data to the data path circuit 25 and receives an instruction code and read data from the data path circuit 26.
The bus controller 35 has an internal bus state counter 36 and outputs a set of external bus control signals 92 to a set of terminals 66 and a set of internal peripheral bus control signals 91 to the peripheral circuits 40 through 49.
The data path circuit 26 is connected through buses 77 and 78 to a set of terminals 65 which are in turn coupled to the external bus 95. The data path circuit 26 is further connected to an internal or incorporated peripheral bus 90 through buses 80 and 81 to output an address and write data to the incorporated peripheral bus and receive read data. The peripheral circuits 40 through 49 are connected to the incorporated peripheral bus 90.
The data path circuit 26 is provided with an instruction queue 50 for storing several prefetched instructions, a prefetch pointer (PFP) 51 for storing prefetching addresses, latches 52 through 56 for latching address/data, and selectors 61 and 62. The latch 52 temporarily latches an address from the CPU 20. The selector 61 selects one of the output 74 of the latch 52, a prefetch address 75 of the prefetch pointer 51 and write data 71 from the CPU 20 outputs to the bus 71, and outputs the selected one to the bus 76 under the control of signals (not shown) from the bus controller 35.
An incrementer 60 outputs the address of the bus 76 incremented by 2 to the prefetch pointer 51. The prefetch pointer 51 memorizes the address from the incrementer 60 and outputs it to the selector 60 through the bus 75. The latch 53 memorizes the address and write data which are on the bus 76 and outputs them to the terminal group 65 through the bus 77. The latch 54 memorizes the read data which was input from the terminal group 65 through the bus 78, and outputs the read data to the instruction queue 50 and the selector 62 through the bus 79.
The instruction queue 50 memorizes the prefetched data on the bus 79 to a plurality of buffers and outputs the memorized data to the CPU 20 through the bus 72 as instruction data. The latch 55 memorizes the address and write data which are on the bus 76 and outputs them to the incorporated peripheral bus 90 through the bus 80. The selector 62 selects either the read data from the external memory on the bus 79 or the read data from the peripheral I/O on the bus 81 and outputs it to the latch 56 under the control of signals (not shown) from the bus controller 35. The latch 56 memorizes the read data from the selector 62 and outputs the read data to the CPU 20 through the bus 73.
Now, the operation of the bus controller 35 will be described.
The bus controller 35 starts the external bus cycle or the incorporated peripheral bus cycle in response to the request 93 from the CPU 20, such as a memory access request, a branch request, and a request to read a queue. The latches 52 through 56, the selectors 61 and 62, and the prefetch pointer 51 within the data path circuit 26 are controlled, and the acknowledge signal 94 is sent to the CPU 20 when the accessing operation is completed.
The bus controller 35 has an internal bus state counter 36, which counts the state of a bus.
Referring to FIG. 10(a) which shows how the external bus cycle and the incorporated peripheral bus cycle make a transition and FIG. 10(b) which shows the state of a service flag for discriminating bus cycles, T1 represents a state where an address is output, T2 represents a state where data is output or input, and T3 represents the end state of a bus cycle or a state where a bus cycle has not been started. These states make a transition in synchronization with the system clock in the microcomputer 12.
The bus controller 35 has service flags SBRSVF 110, FETSVF 111, MEMSVF 112, and IOMSVF 113 in correspondence with the bus state counter 36 to be used for identification of bus cycle types. The SBRSVF 110 goes to a 1 when a branch cycle is executed, and the FETSVF 111 goes to a 1 when a fetch cycle is executed. The MEMSVF 112 goes to a 1 when an external memory access cycle is executed. The IOMSVF 113 goes to a 1 when a peripheral I/O access cycle is executed. When no bus cycle is started, all service flags 100 through 113 go to a 0. The SBRSVF 110, the FETSVF 111, and the MEMSVF 112 represent the bus cycles on the external bus 95, while the IOMSVF 113 represents the bus cycle on the incorporated peripheral bus 90.
First, in a reset state the bus state goes to T3. Until the request 93 from the CPU 20 becomes active, the bus state remains T3. When the request 93 is made active, the bus state makes a T3-to-T1 transition. A T1-to-T2 transition is made unconditionally. If a wait request is made in the state of T2, then the bus state will remain T2. If no wait request is made, a T2-to-T3 transition will be made.
Next, if the request 93 from the CPU 20 becomes active, the bus controller 35 will start a bus cycle. In a case where another bus cycle has already been started, the start of a new bus cycle is made to wait until the bus cycle being started ends.
When a bus cycle is started in response to the memory request 93 from the CPU 20, the bus controller 35 discriminates the external memory access and the peripheral I/O access in accordance with the address. In the case of the external memory access, MEMSVF 112 is set to a 1, and in the case of the peripheral I/O access, IOMSVF 113 is set to a 1.
The bus controller 35 also sets SBRSVF 110 to a 1 when a bus cycle is started in response to the branch request 93 from the CPU 20.
Incidentally, even when there is no request 93 from the CPU 20, the bus controller 35 starts an instruction fetch cycle which fetches an instruction from the external memory 100, as long as the buffer of the instruction queue 50 is not filled up. In this case, FETSVF 111 is set to a 1.
The bus controller 35 discriminates bus cycles, based on the values of the service flags 110 through 113, and in accordance with the kind of a bus cycle, the bus controller 35 controls the latches 52 through 56, the selectors 61 and 62, and the prefetch pointer 51 within the data path circuit 26.
Referring to FIG. 11 which is a timing diagram when the M1 and M2 addresses of the peripheral I/O circuit are accessed and read while fetching an instruction from the N address of the external memory, in this example all bus cycles are not waited.
When an instruction fetch cycle 1 is started, FETSVF 111 representative of a fetch cycle is set to a 1. In the T1 state, the selector 61 selects the bus 75 having the prefetched address N thereon, and the latch 53 fetches the address N and then outputs it to the external bus 95. The prefetch pointer 51 memorizes, at the timing of the end of the T1 state, the address N+2 incremented by+2 by the incrementer 60. In this example, fetching of instructions is performed at units of 2 bytes.
In the T2 state, the latch 54 latches the data n, transferred from the external memory 100 to the external bus 95, and then the data n is fetched into the instruction queue 50. An instruction code, stored in the instruction queue 50, is fetched by the CPU 20 according to the internal instruction process.
The T3 state is the end state of the bus cycle.
Assume now that the CPU 20 made a peripheral I/O circuit accessing request at T1 of the instruction fetch cycle 1. Because the bus controller 35 has priority of an external memory access cycle and a peripheral I/O access cycle over an instruction fetch cycle, the next bus cycle goes to the peripheral I/O access cycle. The bus controller 35 waits for the end of the instruction fetch cycle 1 and then resets FETSVF 111 to a 0 and sets IOMSVF 113 to a 1. The bus controller 35 also switches the control of the data path circuit 26 to a control for a peripheral I/O access cycle.
In the T1 state of the peripheral I/O access cycle, the selector 61 selects the bus 74 which has an address M1 to be accessed. The latch 55 fetches the address M1 and then outputs it to the incorporated peripheral bus 90. At this time, the prefetch pointer 51 does not update an address.
In the T2 state, the data m1, transferred from the peripheral I/O circuit to the incorporated bus 90, is fetched into the latch 56 through the bus 81 by controlling the selector 62. The data m1 fetched in the latch 56 is read in by the CPU 20.
The T3 state is the end state of a bus cycle. In this state, the bus controller 35 outputs the acknowledge 94, which indicates to the CPU 20 that the peripheral I/O access cycle has ended.
Since the peripheral I/O access cycle has ended, the cycle goes to an instruction fetch cycle again. When the instruction fetch cycle 2 is started, IOMSVF 113 is reset to a 0 and FETSVF 111 is set to a 1. Thereafter, as with the instruction fetch cycle 1, data n2 is read from the N+2 address of the memory 100 and is fetched into the instruction queue 50.
Assume now that, during the instruction fetch cycle 2, the CPU 20 again made a request to access the peripheral I/O circuit. The bus controller 35 again resets FETSVF 111 to a 0 and sets IOMSVF 113 to a 1, thereby starting the peripheral I/O access cycle 2. The bus controller 35, as with the peripheral I/O access cycle 1, switches control and reads data, m2, from the M2 address of the peripheral I/O circuit.
In the conventional data processor described above, the incorporated bus state counter 36 of the bus controller 33 comprises a single bus state counter. Therefore, when the external bus cycle and the incorporated peripheral bus cycle are both started, they are to be executed one by one. That is, both of them cannot be executed at the same time.
Therefore, the start of the peripheral I/O access cycle is made to wait until the instruction fetch cycle being started ends. In addition, because of the start of the peripheral I/O access cycle, the instruction fetch cycle was interrupted.
In a build-in data processor, particularly, in a case where a microcomputer is used of the Reduced Instruction Set Computer (hereinafter referred to a RISC) type where a load/store instruction is a basic instruction, sometimes the memory access instruction occupies, for example, 50% of all instructions and also 25% is occupied by the memory access with respect to the peripheral I/O circuit. In such a case, when an instruction of 1/4, that is, 25% of all instructions is executed, the duty rate of the bus is reduced because both the external bus cycle and the incorporated peripheral bus cycle cannot be executed at the same time, resulting in a reduction in the processing ability of the system.